1. Field of the Invention
The present invention relates to a semiconductor device employing SiC and a method of manufacturing the same.
2. Description of Related Art
In recent years, employment of SiC (silicon carbide) as the next-generation power device material implementing low on-resistance has been examined.
A trench gate structure is known as a structure for refining a power device and reducing on-resistance. For example, a power MOSFET employing the trench gate structure is increasingly forming the mainstream.
FIG. 11 is a schematic sectional view of a conventional semiconductor device having a trench gate VDMOSFET employing SiC.
A semiconductor device 201 has a structure obtained by arranging a plurality of unit cells of a trench gate VDMOSFET in the form of a matrix.
The semiconductor device 201 includes an N+-type SiC substrate 202 forming the base of the semiconductor device 201. An N−-type epitaxial layer 203 made of SiC (silicon carbide) doped with an N-type impurity in a lower concentration than the SiC substrate 202 is laminated on an Si surface (a silicon surface) of the SiC substrate 202. A base layer portion of the epitaxial layer 203 forms an N−-type drain region 204 maintaining a state after epitaxy. In the epitaxial layer 203, a P-type body region 205 is formed on the drain region 204 in contact with the drain region 204.
A gate trench 206 is dug down in the epitaxial layer 203 from a surface 217 (an Si surface) thereof. The gate trench 206 passes through the body region 205 in the thickness direction, and the deepest portion (a bottom surface 216) thereof reaches the drain region 204.
In the gate trench 206, a gate insulating film 207 made of SiO2 is formed on the overall regions of the inner surfaces of the gate trench 206 by thermally oxidizing side surfaces 214 and the bottom surface 216 of the gate trench 206.
A gate electrode 208 is embedded in the gate trench 206 by filling up the inner side of the gate insulating film 207 with a polysilicon material doped with an N-type impurity in a high concentration.
On a surface layer portion of the epitaxial layer 203, N+-type source regions 209 are formed on both sides of the gate trench 206 in a direction (the right-and-left direction in FIG. 11) orthogonal to the gate width. The source regions 209 extend along the gate trench 206 in a direction along the gate width, and bottom portions thereof are in contact with the body region 205 from the side of the surface 217 of the epitaxial layer 203.
The epitaxial layer 203 is further provided with P+-type body contact regions 210 passing through central portions of the source regions 209 in the direction orthogonal to the gate width from the surface 217 thereof to be connected to the body region 205.
An interlayer dielectric film 211 made of SiO2 is laminated on the epitaxial layer 203. A source wire 212 is formed on the interlayer dielectric film 211. The source wire 212 has a nickel silicide layer 218 in contact with the source regions 209 and the body contact regions 210 through a contact hole 213 formed in the interlayer dielectric film 211 and an aluminum layer 219 formed on the nickel silicide layer 218.
A drain wire 215 is formed on the rear surface (a carbon surface: a C surface) of the SiC substrate 202. The drain wire 215 has a nickel silicide layer 220 in contact with the SiC substrate 202 and an aluminum layer 221 formed on the nickel silicide layer 220.
A prescribed voltage (a voltage of not less than a gate threshold voltage) is applied to the gate electrode 208 while a prescribed potential difference is caused between the source wire 212 and the drain wire 215 (between a source and a drain), whereby a channel is formed in the vicinity of the interface between the body region 205 and the gate insulating film 207 due to an electric field from the gate electrode 208. Thus, a current flows between the source wire 212 and the drain wire 215, and the VDMOSFET is turned on.